An arrangement of a prior art decision feedback equalization circuit will be explained in connection with FIG. 1.
In a digital signal transmission system, a signal received through a transmission line generally comprises a transmitted signal distorted by intersymbol interference and noise.
The received signal passed through a transmission system with a relatively narrow band as transmission band has such intersymbol interference that affects the previous and subsequent transmission bits. In this specification, such interference which affects bits of the received signal at times antecedent to a received bit will be referred to as the forward interference, while such interference which affects bits of the received signal at times subsequent to the received bit will be referred to as the backward interference.
Noise is a general term for random disturbances independent of signals. For the purpose of removing intersymbol interference from such a received signal, an equalization circuit is used, A decision feedback equalization circuit comprises a linear equalizer 2 for eliminating forward interference in bits of the received signal, an intersymbol interference estimator 80 for eliminating backward interference in the signal bits, a subtracter 4, and a detector 6.
Explanation will next be made as to the operational principle of the decision feedback equalization circuit by referring to FIG. 2. To simplify explanation, it is herein assumed that a received signal 1 received in the decision feedback equalization circuit is a digital data signal of levels "0" and "1" distorted by intersymbol interference and disturbance. It is further assumed that a transmitted signal 33 is an isolated impulse signal having a level "1" at a transmission time corresponding to a reception time k and a level "0" at the other times. The received signal 1 is first subjected at the linear equalizer 2 to removal of forward interference antecedent to the received time k. The received signal is then subjected at the subtracter 4 to subtraction of a feedback signal 9. The feedback signal 9 is an estimate of the backward interference from the currently received bit and the backward interference is removed by subtracting the backward interference estimate for the subsequent bits. Whether to perform the subtraction for removal of the backward interference for the subsequent bits is determined by a decision signal "0" or "1" of the detector 6. That is, when determining the presence of an impulse signal at the received time k, the detector 6 performs a backward interference removing operation over the subsequent bits; whereas, when determining the absence of an impulse signal, the detector 6 performs no backward interference removing operation. The detector 6 generates a detected signal 7 as its output result and applies it to the intersymbol interference estimator 80. An output 9 of the intersymbol interference estimator 80 corresponds to an estimate of the backward interference contained in a signal to be next received from the past received data sequence. The feedback signal 9 generated by the intersymbol interference estimator 80 is applied to a minus input of the subtracter 4 to remove the backward interference applied to the next-received signal. Thereafter, these operations are repeated. An example of such a decision feedback equalization circuit is described in, for example, Jan W. M. Bergmans, "Decision Feedback Equalization for Magnetic Recording Systems", IEEE Trans. Magn. pp. 683, Vol. 24, No. 1, January, 1988.
The timing of operation of the prior art decision feedback equalization circuit is shown in FIG. 3. A main clock period 24 is a period with which a received signal is applied to the decision feedback equalization circuit. It is impossible to set the main clock period 24 to be shorter than a time 25 corresponding to a total sum of a delay time 17 of the subtracter 4, a delay time 18 of the detector 6 and a delay time 19 of the intersymbol interference estimator 80.
In a digital data transmission field, a higher data transmission rate has been always demanded. When a decision feedback equalizer is used as an equalizing means, a decision result is used to estimate an interference and a negative feedback circuit is provided at an input of a decider or detector, which results in that it is impossible to set a data transmission period to be shorter than a delay time of the feedback circuit. Accordingly, for the purpose of shortening the delay time of the feedback circuit to increase the data transmission rate, elements constituted of the feedback circuit are required to be of a high speed type.
It is therefore an object of the present invention to provide an inexpensive, high-speed decision feedback equalization circuit in which a feedback circuit can be made fast in operation while eliminating the need for requiring all elements of the feedback circuit to be of a high speed type.